In recent years, ultralarge-scale integrated (ULSI) circuit devices for use in digital home electronics appliances, personal computers (PCs), mobile cellular phones and others are under requirements for higher integration and higher speed performance. Known basic circuit elements making up such ULSI devices are metal oxide semiconductor (MOS) transistors. See FIG. 8, which depicts a cross-sectional view of a prior known standard MOS transistor. As shown in FIG. 8, this transistor has a silicon (Si) substrate 207, a shallow trench isolation (STI) insulator 208 which is formed in a substrate surface for electrical separation between elements, a gate insulation film 205, a patterned gate electrode 202, sidewall spacers 203, and low resistance layers 206 which are formed by ion implantation on the opposite sides of the gate electrode and which function as source and drain regions.
The gate insulator film 205 may typically be an SiO2 or SiON film, whereas the gate electrode 202 is made of ion-doped polycrystalline silicon (poly-Si). Regarding respective regions of the gate electrode 202 and source/drain 206 along with extension regions 204 and a channel 209, the carrier mobility of the channel and the gate electrode's work function plus electrical resistivities are controllable by appropriately varying the species and dose of dopant ions and also changing anneal conditions after ion implantation. Whereby, it is possible to fabricate N-channel MOS (NMOS) and P-channel MOS (PMOS) transistors on the same Si substrate while suppressing the so-called “short channel” effect.
A size 210 of the gate electrode 202 of the MOS transistor having the above-stated structure is a critical dimension (CD), so it becomes necessary to microfabricate it with high precision. A currently available common approach to forming the gate electrode 202 is to employ a method having the steps of forming a film of electrode material, depositing thereon a resist film, exposing a circuit pattern, and applying dry etching thereto.
An approach to achieving the dry etching is to use a method for converting a reactive gas into a plasma by electromagnetic waves or else and utilizing ion-assisted reaction due to ions and neutral radicals in the plasma. Several types of apparatus used for the dry etching are known, including etcher tools of the capacitive coupled plasma (CCP) type, inductive coupled plasma (ICP) type and electron cyclotron resonance (ECR) type, which are different from one another in plasma creation mechanism. The electromagnetic waves for use with the CCP and ICP etchers are set to 13.56 and 27 MHz, respectively; ECR etcher is designed to use microwaves with a frequency of 2.45 GHz or alternatively ultra-high frequency (UHF) waves of about 450 MHz.
The dry etching apparatus is equipped with a reactive gas introduction mechanism, a plasma processing pressure controlling mechanism, a lower-electrode mechanism for mounting a Si wafer with a to-be-etched film being formed thereon, a Si wafer conveyance/transfer mechanism, and a control module for controlling operation timings of these mechanisms. The lower-electrode mechanism includes an electrostatic chuck (ESC) unit for immovably holding the Si wafer, a Si wafer temperature control unit, and a radio frequency (RF) bias applying unit for attraction and indraft of ions in a plasma.
In the etching apparatus with the above-noted mechanisms, in order to accurately control the size (CD) of gate electrode, it is required to adjust several system parameters (parameter set), such as the kind of a reactive gas, a processing pressure, an output power of electromagnetic wave for plasma creation, a workpiece temperature, an RF bias output power, etc. Consequently, not only in case the to-be-etched film is a multilayered film but also in case this film is made of the same material, there is often performed a multi-step process which adequately switches between prespecified system parameter sets when processing nearby portions of its underlayer boundary or interface.
In the case of performing the multi-step processing, the timing of switching between steps is determined based on a change with time of light emission intensity of molecules or radicals in the plasma or a time change in film thickness interference light. For example, in case a single film is etched, basic steps are a main etching (M.E) for vertically processing most part of a material and over-etching (O.E) for removing residue film components, which steps are used while being switched alternately.
Incidentally, ULSI devices are required to offer low power consumption in addition to the requirements for high integration and high speed performance. A currently investigated means for realizing this low power consumption is as follows. In the case of the MOS transistor shown in FIG. 8 for example, the gate insulator film 205 is made of a specific material with its dielectric constant k being higher than that of SiO2—known as “high-k” material. Examples of this high-k material are ZrO2, Y2O3, La2O3, LaAlOx, LaSiOx, Al2O3, HfO2, HfAlO(N), and HfSiO(N).
Additionally, in order to further enhance the integration and speed performance, it is also under review to employ a gate electrode using a metallic material (metal gate electrode) in place of the poly-Si gate electrode 202 which has difficulty in depletion-layer suppression. One known example is a p-channel MOS (PMOS) device of the type having a multilayer structure of TaSiN and TiN plus HfO2 films. Other examples are an NMOS device of the type having a multilayer of TaSiN and HfO2 films, and a complementary MOS (CMOS) device having stacked W and SiON films with a TiN film interposed therebetween. As for the gate insulator film, there is known a device using HfSiON other than the traditional dielectric materials, such as SiO2 and SiON.
The TiN, which is an expecting material for use as metal gate electrodes, has been traditionally used as a barrier layer of aluminum wiring leads in the form of a multilayer structure of a resist, TiN, Al, TiN and SiO2 films. For etching the TiN film, a plasma has been used which is created using a Cl2 gas with a BCl3 gas or 3% of CH4/Ar gas and/or fluorocarbon gas being added thereto. In this case, it is known that adding a F-based gas such as CHF3 or else to the Cl-based gas such as Cl2/BCl3 results in an increase in etching rate of TiN.
In case the TiN that has been used in metal wiring processes as stated above is used for the gate electrode, a need is felt to perform the etching while realizing the required vertical shape and, at the same time, sufficiently retaining the selectivity relative to the underlying gate insulator film. An approach to attaining this process is disclosed in JP-A-2004-519838, which teaches a two-step etch technique for performing main etching by use of a Cl2 or F-based gas (CF4, CxHyFz) during etching of a TiN/HfO2 metal gate structure, and, after completion of the main etching of TiN, applying overetching to nearby portions of the underlayer interface by using a Cl2/HBr gas.